In a known structure of a self-aligned-gate depletion mode field effect transistor (SAG-DFET) formed on a compound semiconductor substrate, (e.g. a GaAs wafer), a multilayer metal gate structure is provided. The gate structure comprises, for example, a lower layer of a refractory metal silicide, e.g. tungsten silicide, to form a Schottky gate contact with the substrate, and an upper layer of refractory metal, i.e. tungsten to reduce the gate resistance. The multilayer gate structure is typically formed by blanket deposition of layers of tungsten and tungsten silicide overall, and then selectively removing the tungsten/tungsten silicide layers from the semiconductor substrate to leave a gate structure.
For example, a conventional known gate formation process comprises the following steps:
chemical preclean of the substrate surface; PA1 sputter deposition of the Schottky gate metal stack e.g. tungsten silicide and tungsten; PA1 deposition of a photoresist bilayer and patterning to define openings for a gate etch mask PA1 formation of a metallic gate etch mask, e.g. Al, by evaporation, PA1 photoresist strip; PA1 etching of the gate metal stack by high energy plasma etching; PA1 removal of the metal gate etch mask from the gate structure. PA1 providing a semiconductor substrate having a planar surface; PA1 preparing the surface by providing a surface layer of a material which is weakly bonded to the surface; PA1 providing thereon a multilayer masking stack comprising a first masking layer of a material which may be etched selectively relatively to the substrate, and a second layer which has differential etch selectivity relative to the first masking layer; PA1 patterning and etching the multilayer masking stack to define an opening for formation of a device structure on the substrate surface, the differential etch selectivity of the first and second masking layers providing for controlled undercutting of first masking layer relative to the second masking layer, to provide a device opening with undercut sidewalls, and exposing the underlying substrate within the opening; PA1 depositing overall at least one layer of conductive material to form a contact with the substrate within the device opening, said at least one layer of conductive material thereby being deposited on the substrate surface within the device opening and over the surface of the multilayer masking stack, and the undercut sidewalls of the device opening causing a discontinuity in the at least one layer of conductive material, near the sidewall; PA1 etching the at least one layer of conductive material, whereby etching occurs preferentially at the discontinuity near the sidewall and separates part of the at least one layer of conductive material to form a device structure on the substrate surface, thereby separating said part from surrounding parts of the at least one layer of conductive material and the underlying masking layers; PA1 and then, removing the masking layer stack with the overlying conductive material by a lift-off process in which said layers are separated from the substrate at the weakly bonded surface layer. PA1 Thus method is based on a lift-off masking step which avoids blanket deposition of gate metal which would require etching of metal from the substrate. The method makes use of controlled adhesion of a multilayer masking stack on the substrate to provide for a novel application of a lift-off process to form semiconductor device structures. Preferably the masking layer stack comprises non-polymeric, heat resistant materials, other than conventional lift-off polymers, so that the device structure may be formed using metal deposition at elevated temperatures. Thus the method may be used for device structures formed with sputtered or CVD metals , e.g. using a masking layer stack comprising silicon and silicon dioxide or other materials described below. PA1 providing a semiconductor substrate having a planar surface; PA1 preparing the substrate by providing a surface layer of a material which is weakly bonded to the substrate; PA1 providing thereon a multilayer masking stack comprising a first masking layer of a material which may be etched selectively relatively to the substrate, and a second layer which has differential etch selectivity relative to the to the first masking layer; PA1 patterning and etching the multilayer masking stack to define opening for a gate structure on the substrate surface, the differential etch selectivity of the first and second masking layers providing for controlled undercutting of first layer relative to the second layer to provide a gate opening with undercut sidewalls exposing the underlying substrate within the opening; PA1 depositing overall at least one layer of a conductive material to form a contact with the substrate within the gate opening, the at least one layer of conductive material thereby being deposited on the substrate surface within the gate opening and over the surface of the composite mask stack, and the undercut sidewalls of the gate opening causing a discontinuity in the deposited metal layers near the sidewall; PA1 etching the at least one conductive layer, whereby etching occurs preferentially at the discontinuity, separating part of the conductive layers forming a gate structure from surrounding parts of the at least one conductive layer and the underlying masking layers; PA1 and then, removing the composite masking layer with the overlying conductive layers by a lift-off process, in which said layers are separated from the substrate at the weakly bonded surface layer. PA1 a device structure comprising a multilayer stack of conductive materials extending from the surface of a semiconductor substrate, the gate stack being characterized by smooth tapered sidewalls substantially without undercut. PA1 a multilayer gate stack extending from the surface of a semiconductor substrate, the multilayer gate stack being characterized by smooth tapered sidewalls substantially without undercut.
However, it was found that some FETs with etched gates suffered from highly variable breakdown voltages and insufficient current carrying capability.
These effects are associated with a number of problems commonly encountered during this process sequence, particularly relating to the etch process. These problems include gate undercut due to overetching, because the underlying tungsten silicide may etch preferentially to the tungsten layer. An LDD (lightly doped drain) region under the resulting tungsten overhang cannot be sufficiently implanted (i.e. doped) to maintain low channel resistance. Also, subsequent interconnect step coverage is poor when the gate sidewalls are undercut.
On the other hand, underetching may leave metal residues of tungsten and tungsten silicide on the substrate surface. These residues lead to low breakdown voltages. Furthermore, the etch process may leave rough gate edges, which leads to variability in the breakdown voltage. Wide gates have lower breakdown voltages than narrow gates, due to a larger number of edge defects present.
Moreover, the substrate surface suffers ion bombardment during the gate etch. Since the metal layers of the gate stack are blanket deposited overall, the total thickness of the excess metal layers around the gate structures must be removed from the substrate surface around the gate structure. The required high energy plasma etch causes surface damage in the active region surrounding the gate. This surface damage may cause dopant neutralization and lead to current pinch off, and gain variations.
Interactions between these effects lead to devices with unpredictable behavior and poor reliability.
On the other hand, alternative gate etch processes are limited by the available etch chemistries suitable for selectively etching tungsten and tungsten silicide on compound semiconductor substrates.
Refractory metals, e.g. tungsten and titanium are preferred for this application because they are chemically stable and withstand heat cycling at elevated temperatures in subsequent process steps, e.g. annealing to activate dopant in the source/drain regions. Tungsten/tungsten silicide is an existing and proven gate metallurgy for FETs on compound semiconductor substrates.
Typically, a high energy plasma etch, e.g. a CF.sub.4 /.sub.2 etch gas mixture at a high bias, .about.400 eV is a preferred etch for a tungsten/tungsten silicide gate metal snack. Although this etch results in some undercut, the etch uniformity across wafers is typically better than that obtained with alternatives, e.g. an SF.sub.6 /O.sub.2 plasma etch.
Sputtered metal films are preferred over evaporated metal films because evaporated metal films suffer from high tensile stress. Compound semiconductors such as GaAs are piezoelectric and thus are particularly susceptible to stress related doping effects when high stress evaporated metal films are deposited on the semiconductor surface. Sputtering provides a more convenient deposition process, in which the stress in the deposited film can be better controlled during deposition, e.g. by controlling the deposition pressure.
An alternative approach to gate fabrication which has been used with evaporated metals is known as a polymer lift-off process. For example a process is described in U.S. Pat. No. 4,814,258 to Tam, entitled "A PMGI bi-layer lift-off process" in which a polymer bi-layer is used as a mask. After evaporation of the metal, which has a low step coverage, the polymer mask is separated from the substrate, e.g. by a solvent soak, and then lifted off leaving the evaporated metal film in selected areas on the substrate. However, known polymers used for conventional lift-off masks cannot with stand the higher temperatures, i.e. .gtoreq.300.degree. C. as required for deposition of sputtered metals. Not only is there a problem with the polymers softening or melting, and therefore losing dimensional stability, there is also a risk of contamination of the substrate by polymer residues. Thus known lift-off polymer processes are unsuitable for higher temperature deposition of refractory metals by sputtering or chemical vapour deposition (CVD).